Employment Experience

Marvell Semiconductor Inc., Austin, Texas

Cellular and Handheld Group - Application Processor (2005-Present)

Sr. Validation Engineer

· Provided debug support for the following peripheral blocks: Services, Power Management Unit, MSL, I2C, One Wire, SSP, NAND Controller, Static Memory Controller, and Interrupt Controller.

· Created/Modified testplans, testcases, checkers, and trackers for the above modules.

· Provided validation cost for architecture and design changes to the above modules.

· Validated NAND and Static memories. Incorporated denali memory models to the testbench, structured task calls based on memory documentation to sequence reads/writes and other supported functions.

· Worked in conjunction with Israel design/validation team on the Services module to verify new services functionality for Tavor P and Tavor PV devices.

Intel Corporation Wireless and Communication Group, Austin, Texas

Cellular and Handheld Group - DSP Design (2000-2005)

Sr. Validation Engineer

· Implemented design and validation flows for multi-site design teams. Worked with tools team to create a database management tool for design development. (ADAM).

· Worked with the validation team to create a random mnemonics generator (written in object oriented PERL) to validate MSA core.

· Responsible for validating the MSA Core Gasket validation (bus arbiter). Created to ensure functional coverage of the corner cases.

· Responsible for debug support for the MSA Gasket, SSP, Data and Instruction Caches and Memories.

Texas Instruments Semiconductor Group DSP, Houston, Texas

Catalog Digital Signal Processors (1994-2000)

DSP Design Engineer

Test/Simulation

· Provided Validation support for custom design components on chip derivatives

(i.e. memory wrappers, GPIO, HPI, DMA, and Serial Ports)

· Created test cases that validated the scan path and exercised the design for testability (DFT) logic.

· Worked with Japanese Validation team on I/O interface tests in Tokyo, Japan for 3 months.

· Improved on existing TDL generation and validation flows.

· Analyzed chip max transition; max capacitance; and max loading data.

· Analyzed and fixed critical timing paths indicated by static timing analysis.

· Implemented validation flows for single-core and multi-core DSP-chip derivatives

· Managed local and contract validation teams for C2XLP, C5X and C54X product families test case development.

· Improved on existing Design and Validation flows to reducing development cycle time.

· Worked with Product Engineers to debug silicon device functionality and obtain electrical characteristics.

Design

· Responsible for integrating modules into a chip level netlist

· Added new functionality to design rtl and made some Gate Level Fixes.

· Determined module constraints and loading for design modules for synthesis

· Synthesized SRAM memory wrapper modules using Synopsis

· Worked with Application Engineers to define chip functionality.

Education

TEXAS A&M UNIVERSITY, College Station, Texas

Degree: Bachelor of Science in Computer Engineering (May 1994) 3.5 (in major EE & CS Classes) 3.1 overall

Skill Set & Tools

TDL generation, Static Timing Analysis, Spice Simulations, and Test bench Development. Familiar with the following tools: Design Compiler; Simwave; Signalscan; Modelsim; Debussy; Verification Navigator; and PrimeTime. Also familiar with the following languages: C, C++, verilog, VHDL, Perl, Awk, Sed, TI c2xlp, c5x, c54x Assembly, and MSA Assembly.

Hobbies & Interests

Intel Involved, Intel Social Committee, National Association of Asian American Professionals (Board Member), Texas Instruments Chinese Initiative Program (Steering Team), Young Professionals for Children, Youth Leadership Conference (Board Member), Interests in Rock Climbing, Mountain Biking, Skiing, Snowboarding, Tennis, Volleyball, and Golf.

References

Are available upon request.